Digital communication systems are used to transmit data, often at high speeds and over long distances. At a receiving end, a circuit can be used to recover data along with a clock signal embedded in an incoming data stream. Such circuits are generally known as clock and data recovery (CDR) circuits, which recover an embedded clock and retime received data to the recovered clock. Typically, a phase-locked loop (PLL) is used to perform the clock recovery operation.
For many reasons, jitter, which is a fluctuation in the extracted clock signal from a constant rate, can occur. Jitter is to be controlled to reduce performance degradation, and some communication protocols include specifications as to allowable amounts of jitter. Different measures are used to characterize jitter within a system. Measures of jitter include jitter tolerance, jitter transfer and jitter generation.
Jitter tolerance is defined in terms of an applied jitter component whose amplitude, when applied to a system input, causes a certain level of degradation in error performance (e.g., bit error rate). The jitter amplitude is typically measured in unit intervals (UI), where one UI equals a single clock period. Thus jitter tolerance defines the jitter that is to be tolerated by a system when applied to an input of the system.
Jitter transfer is the ratio of the amplitude of a system's output signal jitter to an input signal jitter as a function of jitter frequency. As an example, for CDR circuits a jitter transfer function is typically a low pass filter with a low frequency gain of one. Finally, jitter generation is a measure of jitter at a system's output in the absence of input jitter. Ideally a system should handle significant incoming jitter (i.e., have a high jitter tolerance) while maintaining low jitter transfer and jitter generation levels. However, design tradeoffs exist that frustrate reaching this ideal.
Different communications standards have different requirements for jitter generation, jitter tolerance and jitter transfer. In typical CDR circuits, the jitter tolerance and jitter transfer are determined by the CDR loop bandwidth, and the tolerance and transfer cannot be individually adjusted. As a result, limited clock cleaning opportunities exist in a CDR, as the CDR must operate at the same jitter tolerance and jitter transfer levels.
A typical CDR architecture includes a phase detector to recover the data and to provide phase information that is used to generate a sampling clock. The sampling clock is then provided to a separate clock cleaning module or crystal oscillator to generate a retiming clock based on the sampling clock. However, an external clock cleaning module consumes board space and increases expense.
Furthermore, the clock cleaning module or crystal oscillator typically does not support multiple clock frequencies. As a result, for a single CDR circuit to support different frequencies of operation, multiple oscillators are needed. To support multiple frequency operations, the use of multiple oscillators requires additional board space, increasing size and cost. Furthermore, the oscillator frequency is required to be an integer division of the desired data rate.